In recent years, a three-dimensional type nonvolatile semiconductor memory device has been attracting attention as a nonvolatile semiconductor memory device for achieving a higher degree of integration without being limited by a resolution limit of lithography technology. For example, the following device has been proposed as a three-dimensional type NAND type flash memory, namely, a device comprising: a stacked body having stacked alternately therein on a semiconductor substrate a plurality of conductive films and inter-layer insulating films, the conductive films functioning as a word line or a select gate line; and a semiconductor layer formed so as to penetrate this stacked body. This semiconductor layer functions as a body of a memory string, and there is at least a memory gate insulating layer formed between the semiconductor layer and the conductive film, the memory gate insulating layer including a charge accumulation layer.
This kind of three-dimensional type NAND type flash memory comprises a stepped wiring line portion where the stacked conductive films are formed in steps, for connection to a peripheral circuit. Moreover, a multiplicity of contact plugs are formed so as to extend in a stacking direction from those stepped conductive films. A memory cell array is connected to an external peripheral circuit via these contact plugs and the likes of a higher layer wiring line.
However, the stepped wiring line portion of a conventional three-dimensional type NAND type flash memory has an area that ends up increasing as a stacking number of the memory increases, this leading to an increase in area of a memory chip. Moreover, the increase in stacking number results in the peripheral circuit also increasing in size, and this also leads to an increase in area of the memory chip.